1. Field of the Invention
Embodiments of the present invention relate to manufacturing a semiconductor device including a capacitor (e.g. MIM capacitor) and interconnecting structure using a damascene process.
This application claims the priority of Korean Patent Application No. 2003-52398 filed on Jul. 29, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
As the integration density of semiconductor devices increases in certain applications, increased capacitance of capacitors is required to ensure safe operation of the capacitors. However, a metal-insulator-semiconductor (MIS) capacitor may have the drawback of low capacitance due to a low dielectric constant film between a polysilicon film and a dielectric film. Therefore, a metal-insulator-metal (MIM) capacitor may be used for safer operation.
A MIM capacitor may be connected to peripheral metal interconnecting layers or a drain region of a transistor via contact plugs. An interconnecting structure with interconnected metal interconnecting layers may be formed around the MIM capacitor. The interconnecting structure may be a structure interconnected between an upper metal interconnecting layer and a lower metal interconnecting layer by a contact plug (e.g. a tungsten plug).
Copper may be advantageous as a metal interconnecting material for increasing speed of semiconductor devices. Copper interconnecting can increase reliability of a semiconductor device, since it has a lower electric resistance than aluminum wire and has favorable electromigration characteristics. However, copper interconnecting patterns are generally not formed by an etching process. Rather, copper interconnecting patterns may be formed by a damascene process, because copper can be a difficult material to etch.
In forming an interconnecting structure and an MIM capacitor using a damascene process, difficulty may be encountered in manufacturing vias due to the different depths of vias in the interconnecting structure and the MIM capacitor. For example, a via contacting a lower electrode of the MIM capacitor may be formed prior to forming a via contacting an upper electrode of the MIM capacitor. Accordingly, the metal electrode under the via may be damaged due to different etching depths.
Example FIGS. 1A and 1B are cross-sectional views of a MIM capacitor and an interconnecting structure. In example FIGS. 1A and 1B, lower metal interconnecting layers 11 and 21 act as a lower electrode of the MIM capacitors 10 and 20. The MIM capacitors 10 and 20 include lower metal interconnecting layers 11 and 21, capacitor dielectric films 12 and 22, and upper electrodes 13 and 23. The upper electrodes 13 and 23 of the MIM capacitors 10 and 20 are connected to upper metal interconnecting layers 17 and 27 by contact plugs 15a, 16a and 25a. The lower metal interconnecting layers 11 and 21 act as lower electrodes of the MIM capacitors 10 and 20. The lower metal interconnecting layers 11 and 21 are connected to the upper metal interconnecting layers 18 and 28 by contact plugs 19a and 29a. The contact plugs 15a, 16a, 19a, 25a and 29a are formed by filling the vias 15b, 16b, 19b, 25b and 29b, formed in inter-metal insulating layers 14 and 24, with metal material.
In example FIG. 1A, the upper electrode 13 may be damaged when etching the inter-metal insulating layer 14 to form the via 19b, because the vias 15b and 16b are formed prior to via 19a. The via 19b is formed prior to vias 15b and 16b because the via 19b is deeper than the vias 15b and 16b. For example, when the upper electrode 13 and the lower electrode 11 opened by vias 15b and 16b, a short circuit connection between the upper electrode 13 and the lower electrode 11 may be formed by the contact plugs 15a and 16a. If the upper electrode 13 and the lower electrode 11 are interconnected, the MIM capacitor may not function properly.
The device illustrated in example FIG. 1B has an analogous structure to the device shown in example FIG. 1A. However, a contact plug 25a, connected to an upper electrode 23, is separated from a lower electrode 21. By separating the contact plug 25a from the lower electrode 21, a short circuit connection between the upper electrode 23 and the lower electrode 21, made by the material forming the contact plug, can be avoided even if the via connecting an upper interconnecting layer to the upper electrode 23 is formed through the upper electrode 23 and the capacitor dielectric film 22. Nevertheless, etching damage to the upper electrode 23 through a via 25b can not be completely avoided when etching the via 29b, because the via 29b is deeper than the via 25b. 
Example FIGS. 2A and 2B are cross-sectional views of a device including a MIM capacitor and an interconnecting structure. In the device illustrated in example FIGS. 2A and 2B, in addition to lower metal interconnecting layers 39c and 49c, lower electrodes 31 and 41 of the MIM capacitor are formed. The lower electrodes 31 and 41 are connected to upper metal interconnecting layers 38 and 48 by contact plugs 36a and 46a, respectively.
Referring to example FIGS. 2A and 2B, MIM capacitors 30, 40 (including lower electrodes 31 and 41, capacitor dielectric layers 32 and 42, and upper electrodes 33 and 43) are formed on an insulating layer 5. The upper electrodes 33 and 43 of the MIM capacitors 30 and 40 are connected to the upper metal interconnecting layers 37 and 47 by contact plugs 35a and 45a. The lower metal interconnecting layers 39c and 49c, formed separately from the lower electrodes 31 and 41, are connected to the upper metal interconnecting layers 38 and 48 by the contact plugs 39a and 49a. 
In the device illustrated in example FIG. 2A, a via 39b (for connecting the lower metal interconnecting layer 39c to the upper metal interconnecting layer 38) is deeper than vias 35b and 36b (for connecting the upper electrode 33 and the lower electrode 31 to the upper metal interconnecting layers 37 and 38, respectively). Accordingly, the upper electrode 33 and the lower electrode 31 may be damaged when etching the via 39b since the vias 35b and 36b are formed prior to the via 39b. 
The device illustrated in example FIG. 2B has an analogous structure to the device shown in example FIG. 2A. However, a contact plug 45a (for connecting an upper electrode 43 of an MIM capacitor 40) is separated from a lower electrode 41. By separating the contact plug 45a from an end part of the lower electrode 41, a connection between the upper electrode 43 and the lower electrode 41 by the contact plug material can be avoided, even if the via 45b for connecting an upper metal interconnecting 47 to the upper electrode 43 is formed through the upper electrode 43. However, etching damage to the upper electrode 43 and the lower electrode 41 through the vias 45b and 46b can not be completely avoided when etching the via 49b, because the via 49b is deeper than the vias 45b and 26b. 
In order to solve this problem, research has gone into finding methods of forming a trench in the MIM capacitor in the inter-metal insulating layer so that vias for connecting the MIM capacitor to a metal interconnecting layer can have equal depths. For example, Korea Laid-Open Patent publication 2000-53453 discloses a method of forming a MIM capacitor in a trench having the same depth as an opening for a interconnecting structure using a double damascene method. When the interconnecting structure and the trench for the MIM capacitor are formed to the same depth, a via for connecting the MIM capacitor and a via for connecting the interconnecting structure to respective upper metal interconnecting layer can be formed at equal depths. Also, a capacitance of a semiconductor device can be increased by forming the MIM capacitor in a trench.
However, in this method (of Korean Laid-Open Patent publication 2000-53453), since a portion (for forming the trench of the MIM capacitor) is masked while depositing metal to form a interconnecting structure using a photoresist mask, a selective metal deposition is practically impossible. Electroplating for forming a copper interconnecting structure is generally carried out in a sulfuric acid (H2SO4) based solution. However, photoresist material may be degraded by the sulfuric acid solution. Therefore, the photoresist material for masking the trench portion cannot perform an adequate masking role. The process may be necessarily complicated, because electroplating the interconnecting structure and electroplating the MIM capacitor must be performed separately. Planarization of a copper layer after electroplating may also be difficult, due to the large step.